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Incorporating FIR Filter using MIP Algorithm in Denoising ECG Signal

S. Balasaraswathi, Dr. Meena Srinivasan

Abstract


Transposed direct-form FIR filters which are more effective and realizable structure than direct form are implemented by multiple constant multiplications (MCM) architecture. Early works have focused on replacing MCM blocks by simple operators such as addition, subtraction and shift to form adder-tree. As the complexity of such filters is dominated by the number of additions/subtractions in the adder-tree, common sub expression elimination (CSE) is used by sharing common terms across all multiplications. A novel algorithm in the scheduling of adder-tree operations called mixed integer programming (MIP) algorithm is investigated to enable exact bit-level optimization of adder-trees for efficient FIR filter implementation.

Experimental results shows that upto 4.7% of average area reduction and 3.6% of average power reduction can be achieved on the optimized adder/subtractor tree of the MCM block.


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References


R. Bull and D. H. Horrocks, “Primitive operator digital filter,” IEEE Proceedings-G, vol. 138, no. 3, pp. 401–412, Jun. 1991.

Dong Shi and Ya Jun Yu “Design of Linear Phase FIR Filters with High Probability of Achieving Minimum Number of Adders” IEEE Trans. Circuit Syst., vol. 58, no.1, Jan. 2011.

A. G. Dempster and M. D. Macleod, “Use of minimum-adder multiplier blocks in FIR digital filters,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 42, no. 9, pp. 569–577, 1995.

P. K. Meher and Y. Pan, “Mcm-based implementation of block fir filters for high-speed and low-power applications,” in Proc. VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th Int. Conf., Oct. 2011, pp. 118–121.

R. Mahesh and A. Vinod, “A new common sub expression elimination algorithm for realizing low-complexity higher order digital filters,” IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., vol. 27, no. 2, pp. 217–229, 2008.

Hartley R.I , (1996) “ Subexpression sharing in filters using canonic signed digit multipliers”, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., Vol.43, No. 10, pp.677- 688.

Y. Jang and S. Yang, “Low-power CSD linear phase FIR filter structure using vertical common sub-expression,” Electronics Letters, vol. 38, no. 15, pp. 777-779, July 2002.

Yao C.J.(2004) , “ A novel common sub expression elimination method for synthesizing fixed-point FIR filters”, IEEE Trans. Circuits Syst. I, Vol. 51, no 11, pp 2215-2221.

C.-Y. Yao, H.-H. Chen, T.-F. Lin, C.-J. J. Chien, and X.-T. Hsu, "A novel common-subexpression-elimination method for synthesizing fixed-point FIR filters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 11, pp. 2215 2221, Sep. 2004.

M. M. Peiro, E. I. Boemo, and L. Wanhammar, "Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 3, pp. 196–203, Mar. 2002.

Gustafsson O, “Lower bound for constant multiplication problems,” IEEE Trans. Circuits Syst. II, Exp, Briefs, Vol .54, No.11, pp.974-978, Dec. 2007.

M. B. Gately, M. B. Yeary, and C. Y. Tang, “Multiple real-constant multiplication with improved cost model and greedy and optimal searches,” in Proc. IEEE ISCAS, May 2012, pp. 588–591.

P. Flores, J. Monteiro, and E. Costa, “An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications,” in Proc. IEEE Intl. Conf. Computer-Aided Design, San Jose, CA, Nov. 6–10, 2005, pp. 13–16.

Gustafsson O and Wanhammar L, “Design of linear-phase FIR filters combining sub expression sharing with MILP”, in Proc.MWSCAS’ 02, pp.9-12.

Samueli. H,(1989) “An improved search algorithm for the design of multipliers FIR filters with powers-of-two coefficients “, IEEE Trans. Circuits Syst.,Vol.36, no 7, pp.1044-1047.

Yao. C.Y and Chien C.J, (2002) “A Partial MILP algorithm for the design of linear phase FIR filters with SPT Coefficients”, IEICE Trans. Fundam., Vol. E85-A,pp. 2302-2310.

A. Blad and O. Gustafsson, "Integer linear programming-based bit-level optimization for high-speed FIR filter architecture," Circuits Syst. Signal Process., vol. 29, no. 1, pp. 81–101, Feb. 2010.

M. Yagyu, A. Nishihara, and N. Fujii, “Fast FIR digital filter structures using minimal number of adders and its application to filter design,” ICICE Trans. Fundam. Electron. Commun. Comput. Sci., no. 8, pp. 1120-1129, E79-A, 1996.

P.Prashanti, Dr. B.Rajendra Naik, “Design and Implementation of High Speed Carry Select Adder” International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 9- Sep 2013.

Saranya .S., "Less overhead High performance Adder Tree for FIR Filter Architecture in Speech Processing Applications" IJCSMC, Vol. 3, Issue. 11, November 2014, pg.344 – 350.

Mbachu C.B., Onoh G.N., Idigo V.E., Ifeagwu E.N., Nnebe S.U. “Processing ECG Signal With Kaiser Window- Based FIR Digital Filters” International Journal of Engineering Science and Technology, Vol. 3 No. 8 August 2011 pg no.6775-6783.

Lars Wanhammer, “DSP Integrated Circuits”, copyright @ 1999 by ACADEMIC PRESS.


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