Reversible Logic Implementation for Fused Radix-2 FFT Unit
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Madhusmita Mahapatro, Sisira Kanta Panda, Jagannath Satpathy, Meraj Saheel, M.Suresh, Dr. Ajit Kumar Panda and M K Sukla, “Design of Arithmetic Circuits Using Reversible Logic Gates and Power Dissipation Calculation”, International Symposium on Electronic System Design, 2010.
Dmitri Maslov and Gerhard W.Dueck, “Garbage in Reversible Designs of Multiple Output Functions,”Research supported by the NSERC, Canada.
Himanshu Thapiliyal and Nagarajan Ranganathan, “Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits,” ACM Journal on Emerging Technologies in Computing Systems Vol. V, No. N, Month 20YY.
Anindita Banerjee and Anirban Pathak, “An Algorithm for Minimization of Quantum Cost,”Appl. Math. Inf. Sci. 6, No. 1, 157-165/ www.naturalspublishing.com/amis/,2012.
Cooley, J.W. and Tukey, J.W., An algorithm for the machine calculation of complex Fourier series, Mathematics of Computation, 19(90):297–301, 1965,also in [39].
Keshab K.Parhi, “VLSI Digital Processing Systems: Design and Implementation”, John Wiley, ch 2.
Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler,”Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines”. ISMVL 69-74,2012
Md. Saiful Islam, “A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology,” Institute of Information Technology, University of Dhaka, Dhaka, Bangladesh.
Naveen Kr. Gahlan, Rabhat Shukla and Jasbir Kaur, “Implementation of Wallace Tree Multiplier Using Compressor,” Naveen Kr.Gahlan et al ,Int.J.Computer Technology & Applications,Vol 3,3, 1194-1199.
Niichi Itoh, Yuka Naemura, Hiroshi Makino and Yasunobu Nakase, “A Compact 54x54 Multiplier with Improved Wallace-Tree Structure”, Symposium on VLSI Circuits Digest of Technical Papers, 1999.
N V Vineela Maunika and M Vasuja Devi, “A Dwindled Power and Delay of Wallace Tree Multiplier,” International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 4, October 2012.
S B Rashmi, B G Tilak, B Praveen, “Transistor Implementation of Reversible PRT Gates”, International Journal of Engineering Science and Technology 3: 2289-2297, 2011.
H Thapliyal and N Ranganathan, “A new design of the reversible subtractor circuit”, Proceedings of 11th IEEE International Conference on NanoTechnology, 1430 – 1435, 2011.
Earl E. Swartzlander Jr., Life Fellow,and Hani H.M. Saleh,” FFT Implementation with Fused Floating-Point Operations”, IEEE transactions on computers, vol. 61, no. 2, february 2012.
A.Anjana,” Reversible Logic Implementation of a 54 bit Radix-2 FFT”, Green –ICT‟_13,5th July 2013.
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