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FPGA Implementation of Floating Point Modules for Evaluating Accurate Arithmetic Expression and DSP Applications
Abstract
Recently implementation of floating point modules on FPGA provides acceleration for various applications that requires high performance and high precision floating point arithmetic. Floating point arithmetic in DSP is a more flexible and general mechanism than fixed point. With floating point, system designers have access to wider dynamic range. Today many of the scientific problems are concerned with high precision and energy-efficient floating point arithmetic. With the aim of achieving high precision results and to optimize the speed, in this paper architectures were developed for the evaluation of arithmetic expression using pipelined floating point modules in IEEE 754 formats. Experimental results showed the proposed design resulted in high clock rates compared to the straightforward implementation of floating point module tree architecture and a comparative study was made between SPARTAN 3E and VIRTEX II PRO devices. Additionally the designs can be extended to evaluate general expressions as well as multiple expressions. Such expression evaluations were widely used in embedded computing and digital signal processing applications.
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References
R. P. Brent, “The parallel evaluation of general arithmetic expressions,” J. Assoc. Comput. Mach., vol. 21, no. 2, pp. 201–206, Apr. 1974.
G. L. Miller and J. H. Reif, “Parallel tree contraction and its applica¬tion,” in Proc. 26th IEEE Symp. Foundations Comput. Sci., 1985, pp. 478–489.
G. Govindu, R. Scrofano, and V. K. Prasanna, “A library of parameter¬izable floating-point cores for FPGAs and their application to scientific computing,” in Proc. Int. Conf. Eng. Reconfigurable Syst. Algorithms, 2005, pp. 137–148.
R. Scrofano, L. Zhuo and V.K. Prasanna, “Area-Efficient Arithmetic Exprexxion Evaluation Using Deeply Pipelined Floating-Point Cores,” IEEE Transactions on VLSI systems,vol.16,no.2,pp.167-176,2008.
L. Zhuo and V. K. Prasanna,“Scalable modular algorithms for floating point matrix multiplication on FPGAs,” in Proceedings of the 11th Reconfigurable Architectures Workshop (RAW 2004), April 2004.
IEEE Standard for Binary Floating-Point Arithmetic, 1985, IEEE Std.
L. Louca, T. A. Cook, and W. H. Johnson, “Implementation of IEEE Single precision floating point addition and multiplication on FPGAs,” in Proceedings of the IEEE Symposium on FPGAs for Custom Computing
Machines, April 1996.
P.Belanovic and M.Leeser, “A library of parameterized floating point modules and their use,” in Proceedings of the 12th International Conference on Field Programmable Logic and Applications, M.Glesner, P.Zipf, and M.Renovell, Eds.Berlin: Springer-Verlag, September 2002, pp.657-666.
J. Liang, R. Tessier, and O. Mencer, “Floating point unit generation and evaluation for FPGAs,” in Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, April2003, pp. 185–194.
K. Underwood, “FPGAs vs. CPUs: Trends in peak floating-point performance,” in Proceedings of the 2004 ACM/SIGDA Twelfth International Symposium on Field Programmable Gate Arrays, February 2004.
X. Wang and B. E. Nelson, “Tradeoffs of designing Floating-point division and square root on virtex fpgas,” in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, (Napa Valley, CA), April 2003.
G.Govindu and V.K.Prasanna, “Analysis of high performance floating point arithmetic on FPGAs,” in Proceedings of the 11th Reconfigurable Architectures Workshop (RAW 2004), April 2004.
Z. Luo and M. Martonosi, “Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques,” IEEE Transactions on Computers, vol. 49, no. 3, pp. 208–218, 2000.
Stavros paschalakis and Peterlee, “Double Precision floating-point arithmetic on FPGAs”, in.IEEE Symposium on Field-Programmable Custom Computing Machines, 2003.
M. R. Bodnar, J. R. Humphrey, P. F. Curt, J. P. Durbano,and D. W. Prather. Floating-point accumulation circuit for matrix applications. In Field-Programmable Custom Computing Machines, pages 303–304.IEEE, 2006.
U.Meyer-Baese, “Digital Signal processing with Field Programmable Gate Arrays”, Springer, 2nd edition.
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