A Novel Design of Error-Tolerant Adder for Low-Power High-Speed DSP Applications

Abstract

In this paper a low power structure called Error Tolerant Adder is proposed. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance and Area of chip. When compared to its conventional adder, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.