An Efficient Approach to Designing Low Power Reversible Parallel Binary Adder/Subtractor
In the recent years, Reversible Logic design is attracting more interest due to its low power consumption. Since 1980s Reversible Circuits have gained more attention as components of Quantum algorithms and Nano computing techniques. In this paper, Reversible eight-bit parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. Full adders and Subtractors are realized in a single unit in all three designs. Performance analysis is done based on three criteria: number of gates used, Quantum cost and garbage inputs/outputs. Design III of Reversible eight-bit Parallel Binary Adder/Subtractor is found to be more efficient than Design I, Design II and existing design.
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