Area Minimization of Carry Select Adder Using Boolean Algebra
The requirements of the modern electronic devices are they must be less expensive, compact and have a power saving technology. In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adders as design by O.J. Bedrij is one of the fastest adders used in many data-processing processor. In this adder dual ripple carry adder one for CIN=1 and other for CIN=0 are used. Binary to excess-1 converters are used instead for RCA for CIN=1 in order to enhances the performance of the device. This paper proposes that the size of the adder is featured reduced by using Boolean algebraic techniques.
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