VLSI Architecture for 128×128 Array Multiplier

Abstract

In this paper, low area and low power carry select adder has been designed. This proposed multiplier has many advantages than any other multiplier like power consumption and reduced delay estimation. In this array multiplier, area and speed are the most important design objectives. As a multiplier is the basic operation of all computer arithmetic, multiplier is one of the widely used components in digital VLSI design. Since propagation of carry is of major concern in designing efficient multipliers, this paper presents different multipliers and their performance analysis. Among all the multipliers, the following design provides a good compromise between cost and performance. As Conventional CSLA is more area consuming because of Ripple Carry Adder (RCA), modifications have to be done at the gate level, in order to reduce the area and to increase the speed of operation.