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ASIC Implementation of Efficient Error Detection for Floating Point Addition

K. Kowsalya, A. Janaki, D. Haripriya, V. Nandhini, J. Jayasudha


Floating point operations are used in large dynamic range applications. In a floating point unit addition is one of the most complex operation. An area efficient floating point addition unit with error detection logic is proposed in this paper. Existing error detection logics and leading zero anticipators helps to decrease the delay of the general floating point unit, but they are not area efficient. An area efficient carry select adder with error detection logic is designed by replacing RCA. Here binary to excess-1 converter is used in Carry Select Adder (CSLA) instead of ripple carry adder for carry in = 1. The proposed design is tested on XILINX simulator.

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